General information


Postal Address
TU Dresden
Vodafone Chair Mobile Communications Systems
01062 Dresden

TU Dresden
Vodafone Chair Mobile Communications Systems
Helmholtzstr. 10
01069 Dresden

Visit Address
Office complex Falkenbrunnen
Chemnitzer Str. 50
2nd floor,
01187 Dresden

Thesis Topics Thesis Topics

 Thesis Topics


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Student Project / Diploma Thesis / Master Thesis

Machine Learning for Relay Selection in 5G Ad-hoc Mesh Networks

With Ad-hoc mesh networks, a new decentralized communication system has recently emerged which overcomes the need for additional backbone infrastructure. This allows for new ways of communication and many innovative applications for 5G (e.g., off-the-grid messaging, wireless communication for disaster recovery). Both, reliability and spectrum efficiency are important requirements to enable innovative applications. However, a trade-off between both requirements is inevitable. Relay selection based on machine learning as a tool is expected to provide the optimal saturation for reliability and spectrum efficiency in ad-hoc mesh networks.​

Goal of the thesis:​

  • Performance analysis of Ad-hoc mesh networks with respect to relay selection for cooperative communication,
  • Consider novel approaches such as data-gathering Ad-hoc mesh networks,
  • Design of an efficient relay selection method based on machine learning.​
​Your Skills:​

  • Interested in theoretical work and wireless networks,
  • Basic programming skills in Matlab,
  • Fundamental understanding of mathematics, preferably statistical lerning and information theory. 
  • German or English.

This topic is part of the research project “RESCUE”.​

Contact: Dipl.-Ing. Albrecht Wolf

Student Project

Studies on dynamic coexistence management algorithms for industrial automation

Untersuchungen zu Algorithmen eines dynamischen Koexistenzmanagements für den Einsatz in der Industrieautomation

Im Forschungsprojekt fast automation wird eine Funktechnologie in lizenzfreien Frequenzbändern erforscht und entwickelt, die sich aufgrund extrem niedriger Übertragungslatenzen und hoher Zuverlässigkeit für den Einsatz in der Industrieautomation anbieten soll. Dazu werden an der TU Dresden Algorithmen und Konzepte für ein Koexistenzmanagement mit kooperativer Selbstorganisation erarbeitet. 

Im Rahmen einer Studienarbeit sollen Algorithmen zur Ressourcenallokation ausgewählt und verglichen werden. Dabei sollen eine sehr hohe Zuverlässigkeit sowie die dynamische Adaption an die Umgebung im Mittelpunkt stehen. Darüber hinaus ist die Übertragbarkeit der entsprechenden Architekturansätze auf ein hierarchisches Koexistenzmanagement in Anlehnung an fast automation von Interesse.
Die Studienarbeit umfasst folgende Teilaufgaben:

  • Literaturrecherche zu problembezogenen Algorithmen zur Ressourcenallokation,
  • Auswahl, Implementierung, Dokumentation und Optimierung geeigneter Verfahren,
  • Vergleich im Hinblick auf Zuverlässigkeit und Adaption,
  • Gegenüberstellung der Architekturansätze.

Language: German or English

Contact: Dipl.-Ing. Tom Hößler

Student Project / Diploma Thesis / Master Thesis

Channel Model Framework for Communications Systems in Industrial Environments

For evaluating the performance of different radio air transmission concepts as well as PHY (physical layer) implementation concepts, it is essential to analyze these concepts considering the specific radio propagation characteristics of the operating environments. Therefore, in this work, a flexible channel modelling framework will be developed which can be adapted to different frequency bands and environmental conditions. A special focus is set on channel models for unlicensed frequency bands (below 6 GHz and 60 GHz) which are here used for WLAN-based industrial communications. After the successful implementation of the framework, the results/channel models could be integrated into a laboratory test bed for evaluation of real hardware PHY implementations.

Goal of the thesis:

  • State-of-the-art literature research of existing channel measurements and channel models for industrial environments
  • Design and implementation of a flexible framework for channel model simulation in Matlab
  • Integration of the framework results into a test chain hardware of national instrument (optional)

Your skills:

  • Interested in wireless communications and theoretical work
  • Understanding of radio propagation characteristics (attended MNS I or comparable lectures)
  • Basic programming skills in Matlab
  • First experience with LabVIEW​​


  • German or English

Background information/projects:

In order to replace current wired technologies (e.g. fieldbus systems) in industrial communications networks, new radio air interfaces have to be developed which are capable to guarantee the same transmission (Quality of Service) requirements as the already existing wired solutions. The main challenges here come along with very dynamic and time-dispersive behavior of the propagation channels due to the extraordinary characteristics of industrial environments (e.g. excessive multipath scattering effects due to the abundance of many metallic scatterer, moving metallic objects like robots etc.). Therefore, the goal of the research project proWiLAN is to develop new techniques and methods for wireless local area network technologies in order to address the varying demands of different human-to-machine applications (e.g. augmented reality or mobile panel control) for industrial usage. ​

Contact: Dipl.-Ing. Thomas Augustin

Dr.-Ing. Norman Franchi

Student Project / Diploma Thesis / Master Thesis

Investigation of deadlock recovery schemes in Network-on-chip.

Network-on-chip (NoC) is the highly scalable and bandwidth efficient packet-switched communication network for multi-processor systems-on-chip (MPSoCs). It consists of routers connected to each other via links and arranged in any arbitrary topology. The flit is the smallest unit of transmission is the flow control digit flit. The routing algorithm determines the path of the flit over the NoC from the source to the destination. With deterministic routing, the same path is always followed from a source to a destination and is therefore, quite simple to implement. However, in the presence of faulty components or congested links, adaptive routing is more desirable to bypass faulty links or routers or to balance the load the over network. The switching of packets in the NoC router is wormhole, in which a larger message packet is broken down into smaller flits. The header flit always goes first and then the remaining flits follow in a pipeline fashion, resulting in reduced latency as well smaller storage buffers at the routers. With adaptive routing and wormhole switching, it is possible to have deadlock, a situation in which flits are locked in a dependency cycle. Deadlock causes the network to become blocked as flits cannot move forward.

The task of this thesis is to implement and evaluate deadlock recovery schemes for the mesh and hexagonal NoC topology. For this it is necessary to implement a module to detect the presence of deadlock and to resolve it. The cost of the scheme on the overall network performance i.e. increase in average packet latencies will be evaluated via simulations in a cycle-accurate NoC traffic simulator. Moreover, hardware cost estimates in terms of area and achievable frequency of the deadlock resolution unit will also be estimated.


Contact: M.Sc. EE Sadia Moriam

Diploma Thesis / Master Thesis

Error Rate Model for Multi-Connectivity

​Multi-connectivity (MC) describes system architectures where users are simultaneously connected via multiple communication links. Similar to today’s mobile networks in general, MC techniques have been mainly designed for enhancing data rates, i.e., different information is transmitted over each link (multiplexing gain). However, now with the ascent of 5G development, MC is seen as a critical enabler for achieving high transmission reliabilities, i.e., same information is transmitted over all links in parallel (diversity gain).

In particular, signal processing schemes such as joint decoding, maximum selection combining and maximum ratio combining, can be applied to increase transmission reliability. This work concentrates on joint decoding, since it is known to be optimal.

The performance of MC networks can be assessed by error rates, i.e., frame-error-rate and bit-error rate. To avoid time consuming simulations (including coding, modulation, etc.), the use of error rate models for link performance prediction can be regarded as a common and well-accepted method for protocol- and system-level performance evaluation. Error rate models enable the accurate modeling of instantaneous channel and interference conditions at reasonable computational costs.​

  Goal of this Thesis:

The main focus of this thesis is to develop an error rate model for MC networks. This includes the following subtasks:

  • ​Familiarization with single link error rate models for existing wireless technologies
  • Familiarization with joint decoder and existing simulation framework
  • Development of a MC error rate model based on existing single link error rate models and theoretical MC analysis.
  • Verification of MC error rate model by comparison to existing simulation framework​

Contact: Dipl.-Ing. Albrecht Wolf

Student Project / Diploma Thesis / Master Thesis

Task scheduling / Task clustering

​In modern systems workloads are not performed as a uniformly task but rather than as a composition of thousands diversified tasklets. Consider a LTE base station. For each user signal there must be a FFT, a channel equalization, channel estimation etc.. Each FFT in turn can be split in several hundreds of computation steps.  To perform this actual calculation the tasks have to be scheduled onto one of several available CPUs in a heterogeneous computing platform. For this to happen efficiently, inter task dependencies and computational capacities have to be taken into account. Your project will be the studying of available techniques and algorithms for an efficient task scheduling on heterogeneous computing platforms. Furthermore you will implement the found solutions into an already existing computing engine.

Goals of your work: 

•    Familiarize yourself with existing computing engine
•    Familiarize yourself with task clustering algorithms
•    Find own / or suitable existing algorithm
•    Implement algorithm 

Your skills:

•    Very good C++ knowledge
•    You like to program 
•    Good algorithmic comprehension


•    German or English

Contact: Dipl.-Ing. Robert Wittig

Student Project / Diploma Thesis / Master Thesis

Algorithmen für ARC-Prozessoren

​Im Rahmen der Entwicklung eines Software-Defined-Radio (SDR) Chips, wurde am Vodafone Lehrstuhl in der Vergangenheit die TomaHawk-Plattform entwickelt. Diese wurde seit ihrer Veröffentlichung kontinuierlich weiterentwickelt. Auf der TH-Plattform findet die Umsetzung von komplexen Algorithmen auf ASIPs Xtensa Prozessoren der Firma Cadence statt. Diese sind sogenannte Soft-IP cores, welche die Möglichkeit von individuellen Erweiterungen des Befehlssatzes bieten. Für zukünftige Projekte möchten wir im Rahmen von studentischen Arbeiten die Einsatzfähigkeit von ARC Prozessoren der Firma Synopsys evaluieren. Diese bieten gegenüber den Xtensa Prozessoren die Möglichkeit eigenen Verilog-Code direkt in die Prozessor Pipeline zu integrieren. 

Ziel der Arbeit:  

•    Einarbeitung in die ARC Prozessoren
•    Einarbeitung in vorhandene Algorithmen
•    Umsetzung der Algorithmen auf ARC Prozessoren
•   Benchmarking der Ergebnisse, Vergleich der Performance von ARC und Xtensa

Dich erwarten:

•    Arbeiten in einem jungen, internationalen Team
•    Arbeiten mit industriellen State-of-the-Art Toolflows und Lizenzen
•    Deine Arbeit kann auf Deutsch oder Englisch verfasst werden

Deine Fähigkeiten:

•    Gute bis sehr gute Programmierkenntnisse in C++
•    Gute bis sehr gute Kenntnisse in Verilog oder VHDL
•    Allgemeines Algorithmisches Verständnis
•    Spaß am Programmieren

Contact: Dipl.-Ing. Robert Wittig

Student Project / Diploma Thesis / Master Thesis

ARC algorithms

To enable the next generation of mobile networks and 5G application we at the Vodafone-Chair developed the TomaHawk chip (TH). This is a software defined radio ASIC-ASIP implementation which uses customized instruction set processors to accelerate baseband processing.
In the past we used Xtensa processors from Cadence for our implementations. In the future we would like to evaluate also ARC processors from Synopsys for our needs. For that purpose we are looking for you to help us implement our algorithms on the new platform.

Goals of your work:
•    Get familiar with ARC processors
•    Get familiar with already existing algorithms
•    Port the algorithms to the ARC
•    Benchmarking results

Your benefits:
•    Working in a young, international team
•    Working with state of the art industrial tools

Your skills:
•    Good programming skills in C++
•    Good programming skills in Verilog
•    Algorithmic comprehension

Contact: Dipl.-Ing. Robert Wittig

Diploma Thesis / Master Thesis

Channel Coding under 1-bit Quantization

The continued demand for faster communication systems is driving data rates well beyond 10Gbit/s. E.g., in the HAEC project we investigate the scenario of wireless board-to-board communication, considering data rates of 100Gbit/s at carrier frequencies in the range between 100-300​GHz. However, digitizing the signal with a bandwidth of 10GHz and beyond imposes challenging requirements on the analog-to-digital converter (ADC). Surveys show that power limited high sampling rates come at the price of coarse quantization. Considering this, using an ADC with coarse (1 bit) quantization can be beneficial as the low resolution can be compensated by higher signaling and sampling rates.​ In particular, we use run-length limited (RLL) coding together with faster than Nyquist signaling rates to increase the spectral efficiency beyond 1bit/Hz.

An open problem in the system design is including the channel coding. The property of modern codes to approach capacity, e.g. LDPC codes,  depends heavily on the availability of soft values as input to the iterative decoding algorithm. Hence, the main task will be to investigate how to utilize oversampling under 1-bit quantization, in order to provide the channel decoder with soft information.

Goal of the thesis:

  • get familiar with RLL codes, LDPC codes and SC-LDPC codes
  • ​investigate how to connect channel coding and RLL coding
  • find a way to provide the iterative decoder with soft information
  • evaluate the system performance

Your skills:

  • knowledge in basic coding theory and information theory is very important
  • knowledge in LDPC codes and iterative decoding is a huge plus
  • programming skills
  • interest in a topic that combines theoretical and algorithmic research with practical system simulations
  • ​German or English

Contact: Dipl. Martin Schlüter