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Postal Address
(Letters)
TU Dresden
Vodafone Chair Mobile Communications Systems
01062 Dresden

(Parcels)
TU Dresden
Vodafone Chair Mobile Communications Systems
Helmholtzstr. 10
01069 Dresden

Visit Address
Office complex Falkenbrunnen
Chemnitzer Str. 50
2nd floor,
01187 Dresden

New Website
www.vodafone-chair.org

Thesis Topics Thesis Topics

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Student Project

Studies on dynamic coexistence management algorithms for industrial automation

Untersuchungen zu Algorithmen eines dynamischen Koexistenzmanagements für den Einsatz in der Industrieautomation

Im Forschungsprojekt fast automation wird eine Funktechnologie in lizenzfreien Frequenzbändern erforscht und entwickelt, die sich aufgrund extrem niedriger Übertragungslatenzen und hoher Zuverlässigkeit für den Einsatz in der Industrieautomation anbieten soll. Dazu werden an der TU Dresden Algorithmen und Konzepte für ein Koexistenzmanagement mit kooperativer Selbstorganisation erarbeitet. 


Im Rahmen einer Studienarbeit sollen Algorithmen zur Ressourcenallokation ausgewählt und verglichen werden. Dabei sollen eine sehr hohe Zuverlässigkeit sowie die dynamische Adaption an die Umgebung im Mittelpunkt stehen. Darüber hinaus ist die Übertragbarkeit der entsprechenden Architekturansätze auf ein hierarchisches Koexistenzmanagement in Anlehnung an fast automation von Interesse.
Die Studienarbeit umfasst folgende Teilaufgaben:

  • Literaturrecherche zu problembezogenen Algorithmen zur Ressourcenallokation,
  • Auswahl, Implementierung, Dokumentation und Optimierung geeigneter Verfahren,
  • Vergleich im Hinblick auf Zuverlässigkeit und Adaption,
  • Gegenüberstellung der Architekturansätze.

Language: German or English

Contact: Dipl.-Ing. Tom Hößler

Student Project / Diploma Thesis / Master Thesis

Channel Model Framework for Communications Systems in Industrial Environments

For evaluating the performance of different radio air transmission concepts as well as PHY (physical layer) implementation concepts, it is essential to analyze these concepts considering the specific radio propagation characteristics of the operating environments. Therefore, in this work, a flexible channel modelling framework will be developed which can be adapted to different frequency bands and environmental conditions. A special focus is set on channel models for unlicensed frequency bands (below 6 GHz and 60 GHz) which are here used for WLAN-based industrial communications. After the successful implementation of the framework, the results/channel models could be integrated into a laboratory test bed for evaluation of real hardware PHY implementations.

Goal of the thesis:

  • State-of-the-art literature research of existing channel measurements and channel models for industrial environments
  • Design and implementation of a flexible framework for channel model simulation in Matlab
  • Integration of the framework results into a test chain hardware of national instrument (optional)

Your skills:

  • Interested in wireless communications and theoretical work
  • Understanding of radio propagation characteristics (attended MNS I or comparable lectures)
  • Basic programming skills in Matlab
  • First experience with LabVIEW​​

Languages:

  • German or English

Background information/projects:

In order to replace current wired technologies (e.g. fieldbus systems) in industrial communications networks, new radio air interfaces have to be developed which are capable to guarantee the same transmission (Quality of Service) requirements as the already existing wired solutions. The main challenges here come along with very dynamic and time-dispersive behavior of the propagation channels due to the extraordinary characteristics of industrial environments (e.g. excessive multipath scattering effects due to the abundance of many metallic scatterer, moving metallic objects like robots etc.). Therefore, the goal of the research project proWiLAN is to develop new techniques and methods for wireless local area network technologies in order to address the varying demands of different human-to-machine applications (e.g. augmented reality or mobile panel control) for industrial usage. ​

Contact: Dipl.-Ing. Thomas Augustin

Dr.-Ing. Norman Franchi

Student Project / Diploma Thesis / Master Thesis

Investigation of deadlock recovery schemes in Network-on-chip.

Network-on-chip (NoC) is the highly scalable and bandwidth efficient packet-switched communication network for multi-processor systems-on-chip (MPSoCs). It consists of routers connected to each other via links and arranged in any arbitrary topology. The flit is the smallest unit of transmission is the flow control digit flit. The routing algorithm determines the path of the flit over the NoC from the source to the destination. With deterministic routing, the same path is always followed from a source to a destination and is therefore, quite simple to implement. However, in the presence of faulty components or congested links, adaptive routing is more desirable to bypass faulty links or routers or to balance the load the over network. The switching of packets in the NoC router is wormhole, in which a larger message packet is broken down into smaller flits. The header flit always goes first and then the remaining flits follow in a pipeline fashion, resulting in reduced latency as well smaller storage buffers at the routers. With adaptive routing and wormhole switching, it is possible to have deadlock, a situation in which flits are locked in a dependency cycle. Deadlock causes the network to become blocked as flits cannot move forward.

The task of this thesis is to implement and evaluate deadlock recovery schemes for the mesh and hexagonal NoC topology. For this it is necessary to implement a module to detect the presence of deadlock and to resolve it. The cost of the scheme on the overall network performance i.e. increase in average packet latencies will be evaluated via simulations in a cycle-accurate NoC traffic simulator. Moreover, hardware cost estimates in terms of area and achievable frequency of the deadlock resolution unit will also be estimated.

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Contact: Dr. Sadia Moriam

Student Project / Diploma Thesis / Master Thesis

Task scheduling / Task clustering

​In modern systems workloads are not performed as a uniformly task but rather than as a composition of thousands diversified tasklets. Consider a LTE base station. For each user signal there must be a FFT, a channel equalization, channel estimation etc.. Each FFT in turn can be split in several hundreds of computation steps.  To perform this actual calculation the tasks have to be scheduled onto one of several available CPUs in a heterogeneous computing platform. For this to happen efficiently, inter task dependencies and computational capacities have to be taken into account. Your project will be the studying of available techniques and algorithms for an efficient task scheduling on heterogeneous computing platforms. Furthermore you will implement the found solutions into an already existing computing engine.

Goals of your work: 

•    Familiarize yourself with existing computing engine
•    Familiarize yourself with task clustering algorithms
•    Find own / or suitable existing algorithm
•    Implement algorithm 

Your skills:

•    Very good C++ knowledge
•    You like to program 
•    Good algorithmic comprehension

Language:

•    German or English

Contact: Dipl.-Ing. Robert Wittig

Student Project / Diploma Thesis / Master Thesis

Algorithmen für ARC-Prozessoren

​Im Rahmen der Entwicklung eines Software-Defined-Radio (SDR) Chips, wurde am Vodafone Lehrstuhl in der Vergangenheit die TomaHawk-Plattform entwickelt. Diese wurde seit ihrer Veröffentlichung kontinuierlich weiterentwickelt. Auf der TH-Plattform findet die Umsetzung von komplexen Algorithmen auf ASIPs Xtensa Prozessoren der Firma Cadence statt. Diese sind sogenannte Soft-IP cores, welche die Möglichkeit von individuellen Erweiterungen des Befehlssatzes bieten. Für zukünftige Projekte möchten wir im Rahmen von studentischen Arbeiten die Einsatzfähigkeit von ARC Prozessoren der Firma Synopsys evaluieren. Diese bieten gegenüber den Xtensa Prozessoren die Möglichkeit eigenen Verilog-Code direkt in die Prozessor Pipeline zu integrieren. 

Ziel der Arbeit:  

•    Einarbeitung in die ARC Prozessoren
•    Einarbeitung in vorhandene Algorithmen
•    Umsetzung der Algorithmen auf ARC Prozessoren
•   Benchmarking der Ergebnisse, Vergleich der Performance von ARC und Xtensa

Dich erwarten:

•    Arbeiten in einem jungen, internationalen Team
•    Arbeiten mit industriellen State-of-the-Art Toolflows und Lizenzen
•    Deine Arbeit kann auf Deutsch oder Englisch verfasst werden

Deine Fähigkeiten:

•    Gute bis sehr gute Programmierkenntnisse in C++
•    Gute bis sehr gute Kenntnisse in Verilog oder VHDL
•    Allgemeines Algorithmisches Verständnis
•    Spaß am Programmieren

Contact: Dipl.-Ing. Robert Wittig

Student Project / Diploma Thesis / Master Thesis

ARC algorithms


To enable the next generation of mobile networks and 5G application we at the Vodafone-Chair developed the TomaHawk chip (TH). This is a software defined radio ASIC-ASIP implementation which uses customized instruction set processors to accelerate baseband processing.
In the past we used Xtensa processors from Cadence for our implementations. In the future we would like to evaluate also ARC processors from Synopsys for our needs. For that purpose we are looking for you to help us implement our algorithms on the new platform.

Goals of your work:
•    Get familiar with ARC processors
•    Get familiar with already existing algorithms
•    Port the algorithms to the ARC
•    Benchmarking results

Your benefits:
•    Working in a young, international team
•    Working with state of the art industrial tools

Your skills:
•    Good programming skills in C++
•    Good programming skills in Verilog
•    Algorithmic comprehension

Contact: Dipl.-Ing. Robert Wittig

Student Project / Diploma Thesis / Master Thesis

Neural Network based Sequence Detection for Communication Systems

​​The continued demand for faster communication systems is driving data rates well beyond 10Gb/s. Digitizing the signal with a bandwidth of 10GHz and beyond imposes challenging requirements on the analog-to-digital converter (ADC). Surveys show that power limited high sampling rates come at the price of coarse quantization. Considering this, using an ADC with 1 bit quantization can be beneficial as the low resolution can be compensated by higher signaling and sampling rates, i.e., oversampling w.r.t. the Nyqist rate.

This technique results in ISI and colored Gaussian noise at the receiver. Since it is an open mathematical problem to find an analytical description for the orthant probabilities of a correlated Gaussian vector, an analytical description of the likelihood function of the channel is not know and thus the Viterbi detector cannot be derived. 

Motivated by the recent success of deep neural networks in image classification and detection of sequential data like speech signals, where the underlying mathematical models are unknown, we want to apply deep neural networks for the detection of data sequences in communication systems based on 1-bit quantization and oversampling.

​Thesis Goal:

  • ​literature research of recent NN architectures for sequential data detection
  • apply known architectures or propose new architectures for the detection of data sequences in communication systems based on 1-bit quantization and oversampling
  • evaluate the detection performance for different system settings
Your Skills
  • ​sound knowledge in communication theory
  • basic theoretical knowledge in machine learning and optimization, or the willingness to acquire this knowledge​
  • hands on experience with neural networks are a big plus
  • serious programming skills​
​Language
  • ​​German or English

Contact: Dipl. Martin Schlüter

Student Project / Diploma Thesis / Master Thesis

Digital receiver synchronization under 1-bit quantization: Oversampling vs Overmodulation

The continued demand for faster communication systems is driving data rates well beyond 10Gb/s. Digitizing the signal with a bandwidth of 10GHz and beyond imposes challenging requirements on the analog-to-digital converter (ADC). Surveys show that power limited high sampling rates come at the price of coarse quantization. Considering this, using an ADC with 1 bit quantization can be beneficial in terms of energy consumption, but will cause an information loss at the receiver

The proposed method of 1-bit quantization poses a serious challenge to the design of the digital receiver, since standard synchronization algorithms that rely on high amplitude resolution cannot be applied anymore. Thus, new algorithms to estimate the channel parameters ( e.g., timing, phase and frequency offset) must be derived. The first step is to analyze the fundamental limits of parameter estimation and to derive techniques that reduce the information loss caused by 1-bit quantization. Since under 1-bit quantization the information in a signal lies within the temporal distances of its zero crossings, oversampling w.r.t. Nyquist rate can reduce the information loss. An alternative is sampling several rotated versions of the complex signal at Nyquist rate, called overmodulation. Rotating the signal is equivalent to rotating the complex plane, and thus, overmodulation separates the complex plane into more than 4 bins, which is increasing the information on the phase of the signal. 

Goal of the thesis

  • ​Familiarize yourself with the synchronization in digital receivers
  • Derive the Fisher Information for oversampling and overmodulation under 1-bit quantization
  • Compare oversampling and overmodulation in terms of how much information they can recover
Your Skills

  • Sound knowledge in communication theory
  • Basic knowledge in estimation theory or the willingness to acquire this knowledge
  • Basic knowledge in receiver synchronization or the willingness to acquire this knowledge​

Language

  • ​German or English

Contact: Dipl. Martin Schlüter

Student Project / Diploma Thesis / Master Thesis

Framework development for automated translation of graphical models into C Code

Work can be done in german or english

In the last decades the approach for software development has dramatically changed. Whereas in the past it was sufficient to develop a program in a specific programming language and deploy it on the designated hardware nowadays this approach is not efficient anymore. A single application is required to run on a multitude of systems not only differing in the underlying hardware but also on the use of operating systems etc.. With this, the time for development has exploded. One approach to tackle this problem is the use of higher abstraction levels where a software is described in an intermediate, easy to learn language. After validation the software than gets translated into the target language (e.g. C, Java etc.) automatically.   One of the described intermediate languages can be a visual programming language like Matlab Simulink or LabView. In your project work you would extend an automated framework which takes a LabView program and automatically translates it into C code.

Goals of the work:

  • Familiarize yourself with LabView programming
  • Writing of an XML parser to extract information about a LabView program 
  • Writing of C code for atomic LabView blocks
  • Write C code for communication between blocks
  • Test your system with examples and growing complexity

Your benefits:

  • Working with state of the art industrial tools
  • Working in a young, international team

Your skills:

  • Good C++ knowledge
  • Good python knowledge
  • Good algorithmic comprehension



Contact: Dipl.-Ing. Robert Wittig

Diploma Thesis / Master Thesis

Coding for Channels with 1-bit Quantization and Oversampling

In the design of energy efficient communication systems with data rates beyond 100Gb/s the analog-to-digital converter (ADC) poses a bottleneck in terms of energy consumption. Considering this, using an ADC with 1 bit quantization can be beneficial as the low resolution can be compensated by higher signaling and sampling rates, i.e., over-sampling w.r.t. the ​Nyquist rate. 

​Preliminary studies show that sequence design in combination with faster-than-Nyquist (FTN) signaling is an effective method to increase the spectral efficiency in case of 1-bit quantization. An intuitive choice for sequence design is the so called runlength limited (RLL) encoding, which defines a minimum number of consecutive symbols that must have the same value.

In the design of a practical communication system the design of RLL codes with simple encoding and decoding algorithms becomes vital. A classical approach that is often used in recording systems is the use of lookup tables. However, modern wireless communication systems rely strong channel codes, e.g., Turbo, LDPC or Polar codes, which again rely on soft information. Obviously, soft information can not be carried through a lookup table. Hence, the goal of this thesis is to investigate the more sophisticated method called the state splitting algorithm, which can produce a state machine encoder for any RLL code. Due to this state machine representation, decoding on the receiver side can be performed using the Viterbi algorithm, which can also produce soft information for the subsequent channel decoder.

Thesis Goal
  • Literature research on RLL codes
  • investigate the state splitting algorithm
  • complexity analysis of the obtained RLL codes
  • Implementation of encoder and decoder in Matlab/Python
Your skills
  • sound knowledge in information theory, communication theory and coding theory
  • interest in algorithmic research
  • solid programming skills
Language
  • German or English

Contact: Dipl. Martin Schlüter