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 Markus Winter - Personal Website


 

Dipl.-Ing. Markus Winter 

Postal
Address:

Technische Universität Dresden
Fakultät Elektrotechnik und Informationstechnik
Vodafone Stiftungslehrstuhl
Mobile Nachrichtensysteme
D-01062 Dresden, Germany

Visit
Address:

Barkhausenbau (BAR), Room II/7e (second floor)
Georg-Schumann-Str. 11
01187 Dresden

Phone:

+49 351 463 41 048

Fax:

+49 351 463 41 099

e-mail:

winter@ifn.et.tu-dresden.de

Scientific Interests  |  Vitae  |  Teaching  |  Projects  |  Student Projects  |  Publications 

 


Letzte Änderung: 03/04/2010 13:25:43

Scientific Interests

  • System-on-Chip design and design automation
  • Network-on-Chip design, architecture and design automation/generation
  • Network-on-Chip management and QoS realization

Education, Vitae

Dec. 2005 Diplom-Ingenieur (equivalent to M.Sc.) in Information System Technology (Informationssystemtechnik) at TU Dresden
Sep. 2004 - Feb. 2005 Internship at Texas Instruments Germany in Freising
Dec. 2003 - June 2004 Student Assistant at Vodfone Chair Mobile Communications Systems, TU Dresden
Oct. 2002 - Feb. 2003 Tutor at Faculty for Mathematics and Science, TU Dresden
July 1999 Abitur M.-v.-Ardenne-Gymnasium Riesa

Projects

  • Tommy/Atlas Multi-Processor System-on-Chip developed at Vodafone chair
  • TOMAHAWK Multi-Processor System-on-Chip developed at Vodafone chair

Teaching Courses

  • Winter semester 2008: Praktikum Mikrorechentechnik
  • Summer semester 2008: Übung Einführung in die Nachrichtentechnik (Introduction to communications)
  • Winter semester 2007: Praktikum Mikrorechentechnik
  • Summer semester 2007: Übung Einführung in die Nachrichtentechnik (Introduction to communications)
  • Winter semester 2006: Praktikum Mikrorechentechnik
  • Summer semester 2006: Übung Einführung in die Nachrichtentechnik (Introduction to communications)
  • Winter semester 2007: Nachrichtentechnik Seminar: MRAM, DRAM, SRAM, Flash,... - A Survey on Memory Types
  • Summer semester 2007: Nachrichtentechnik Seminar: PCI and PCI Express Architecture

Student projects

Open Topics

Currently there are no open student projects. If you are still eager about NoC design and research, please contact me via E-mail or directly at the Chair

Running and Finished Student Projects

  • Steffen Prusseit: Student Project, Since March 2010
    Development and Analysis of Routing Algorithms in clustered and hierarchical Networks-on-Chip
  • Friedrich Pauls: Student Project, Since June 2009
    Development and Analysis of Slotted Guaranteed Service Channels in Network-on-Chip
  • 0
    Development and Analysis of a Central Unit for Allocation of Virtual Channels in Networks-on-Chip
  • 09
    Development and Implementation of a USB interface on an FPGA for the Tomahawk project
  • Eric Wünsche: Student Project, Oct. 2008- June 2009
    Development and Implementation of an Ethernet interface on an FPGA for the Tomahawk project
  • Eric Wünsche: Student Assistant and Student Project, Nov. 2007 - August 2008
    Development and Implementation of of I/O and hardware modules (e.g. SDRAM) on an FPGA for the Tomahawk project
  • Lei Zhao: Student Assistant, May 2008 - Oct. 2008
    Development and Analysis of a Routing Mechanism for Network-on-Chips with arbitrary and irregular topologies
  • Jonas Eymann: Student Project, Feb. 2008 - Nov. 2008
    Development and Analysis of Routers with Guaranteed Traffic in Networks-on-Chip
  • Oliver Richter: Student Project, Dec. 2007 - Aug. 2008
    Development and Analysis of Cache Coherence Protocols in Network-on-Chip based System-on-Chips
  • Thilo Vörtler: Diploma Thesis, Oct. 2007 - June 2008
    Development and Analysis of Different Routing Mechanisms and Architectures in Network-on-Chips
  • Luis Francisco Martin Gil: Student assistant, May 2007 - Sep. 2007
    Development of a Network-on-Chip generator as hardware design automation tool and a simulation model for Networks-on-Chip
  • Patrick Grosa: Student assistant, Sep.2006 - Oct. 2006
    Implementation of a Network-on-Chip architecture in Verilog HDL

Supervised Student Seminars

  • Qingqing Xia: June 3, 2008
    A Survey of Design Techniques for System-Level Dynamic Power Management
  • Le Ahn Quang: Nov. 29, 2007
    Verification Techniques for Embedded Processor Design
  • Thomas Klotz: June 5, 2007
    From Algorithm to RTL with SystemC in Hardware Design

Publications

  • E. Matus, T.Limberg, M. Winter, M. Bimberg, R. Klemm, M.B.S. Tavares, H. Ahlendorf and G. Fettweis
    Multi-Processor SDR Platform with HW Supported Dynamic Scheduling,
    In Proceedings of the 12th Symposium on Low-Power and High-Speed Chips (COOLChips'09), Yokohama, Japan, April 15 - 17, 2009.
  • T. Limberg, M. Winter, M. Bimberg, R. Klemm, M.B.S. Tavares, H. Ahlendorf, E. Matus, G. Fettweis, H. Eisenreich, G. Ellguth and J.-U. Schlüssler
    A Heterogeneous MPSoC with Hardware Supported Dynamic Task Scheduling for Software Defined Radio,
    DAC/ISSCC Student Design Contest, San Francisco, CA, USA, February 8 - 12 and July 26 - 31, 2009.
    2009 DAC/ISSCC Student Design Contest Winner.
  • M. Winter and G. Fettweis,
    Interconnection Generation For System-on-Chip Design,
    Presented at Kleinheubacher Tagung, Miltenberg, Germany, September 25
  • - 29,
  • 2

  • Interconnection Architecture For System-on-Chip Design Providing Little Overhead, Low Latency and High Throughput,
    9th EUROMICRO Conference on Digital System Design (DSD), Cavtat/Dubrovnik, Croatia, August 28th - September 1st 2006.